Abstract ⎯ In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/code-segment size for a given application. I
Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most comm...
The classic approach for error correction is to add controlled external redundancy to data. This app...
An application may have different sensitivity to faults in different subsets of the data it uses. So...
In this paper we address the issue of improving ECC correction ability beyond that provided by the s...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
Servers and HPC systems often use a strong memory error correction code, or ECC, to meet their relia...
IEEE 20th International On-Line Testing Symposium (IOLTS) (2014 : Catalunya, SPAIN)Scaling supply vo...
Abstract—With increasing parameter variations in nanometer technologies, on-chip cache in processor ...
Abstract---Error correction codes (ECCs) have been used for decades to protect memories from soft er...
Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Singl...
AbstractCache memories serve as accelerators to improve the performance of modern microprocessors. C...
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. e...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Because main memory is vulnerable to errors and failures, large-scale systems and critical servers u...
Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most comm...
The classic approach for error correction is to add controlled external redundancy to data. This app...
An application may have different sensitivity to faults in different subsets of the data it uses. So...
In this paper we address the issue of improving ECC correction ability beyond that provided by the s...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
Servers and HPC systems often use a strong memory error correction code, or ECC, to meet their relia...
IEEE 20th International On-Line Testing Symposium (IOLTS) (2014 : Catalunya, SPAIN)Scaling supply vo...
Abstract—With increasing parameter variations in nanometer technologies, on-chip cache in processor ...
Abstract---Error correction codes (ECCs) have been used for decades to protect memories from soft er...
Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Singl...
AbstractCache memories serve as accelerators to improve the performance of modern microprocessors. C...
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. e...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Because main memory is vulnerable to errors and failures, large-scale systems and critical servers u...
Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most comm...
The classic approach for error correction is to add controlled external redundancy to data. This app...
An application may have different sensitivity to faults in different subsets of the data it uses. So...