Thermal-Aware, Power Efficient, and Makespan Realized Pareto Front for Cloud Scheduler

Abstract—The performance demands of modern computing applications have enormously accelerated the power density of on-chip devices. Consequently, not only the operational budget has increased exponentially, but also the temperature has expe-rienced an alarming increase rate. The high chip temperatures pose serious threat to devices reliability. The aforementioned chal-lenges necessitate the requirement of realizing efficient mapping methodologies to overcome resource exploitation. We present a convex optimization model that maximizes the power savings while satisfying the task completion deadline and maintaining chip temperature within acceptable bounds. Optimization is achieved by varying the frequency of operation of the core. The salient feature of the devised approach is the bounds of operation for the desired objectives. The acceptable operation limit manifests the elasticity of the computing resources in an autonomic manner to achieve a Pareto front for the optimized solutions. To validate our proposed method, extensive simulations are performed on a variable workload