A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

Leakage power has become one of the most critical design con-cerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power without sacrific-ing performance. In this paper, we present an effective and scalable transistor-level Vth assignment approach and show leakage reduc-tion over standard cell-level Vth assignment. The main disadvan-tage of transistor-level Vth assignment is increased cell library size and characterization effort. In comparison to previous approaches, our approach yields better solution quality, requires smaller cell li-brary, is more accurate in considering the impact of Vth assignment on propagation delay, slew (transition delay) and capacitance, and is significantly faster. 1