7.6 Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing

Wafer-level simultaneous testing (WLST) where all chips on a wafer are tested and burned in at the same time is preferable in reducing the cost of obtaining Known Good Dies (KGD’s). At present, however, it is difficult to realize the WLST because it requires a probe card with some hundred thousand needles, leading to more than a ton of force needed for stable contact of all needles. Non-contact probing has been proposed based on a chip-to-chip inductively-coupled inter-face [1] which can reduce the force but it needs a probing chip built specific to a certain product, which is costly. Recently, a low-cost membrane-based prob-ing technique has been disclosed which makes use of the atmospheric pressure and 700kg of force can be uniformly distributed over a 300mm wafer [2]. Yet, since a contacting bump is used and each bump requires 4g of force, the num-ber of pins is limited to about 150K, which is still the world biggest pin counts ever reported. Figure 7.6.1 shows the proposed WLST system. The contacting bumps can be used not only for power supply but also for testing ultra-high speed interface