3.2 Performance-Impact Limited Area Fill Synthesis *

Chemical-mechanical planarization (CMP) and other manufactur-ing steps in very deep-submicron VLSI have varying effects on de-vice and interconnect features, depending on the local layout den-sity. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the lit-erature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PJL-Fill) problem with the objective of either minimizing total de-lay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solutio