Integrating Abstract NoC Models within MPSoC Design

Current embedded applications are migrating from sin-gle processor-based systems to intensive data communi-cation requiring multiprocessing. The performance de-manded by these applications requires the use of hetero-geneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infra-structures, such as Networks on Chip or NoCs. NoC pa-rameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essen-tial aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Appli-cability of the concepts is demonstrated through two het-erogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder.