BTI-Gater: An Aging-Resilient Clock Gating Methodology

(N/PBTI) have become one of the most important reliability issues in modern semiconductor technology. N/PBTI-induced degrada-tion depends heavily on workload, which causes imbalanced degradation and additional clock skew for clock distribution networks with clock gating features. In this work, we first analyze the effects of N/PBTI on clock paths with different clock gating use cases. Then cross-layer solutions are proposed to reduce N/PBTI-induced clock skew. Two Integrated Clock Gating (ICG) cell circuits are proposed to alternate clock idle state between logic high and logic low for each clock gating operation. A skew mitigation methodology is also proposed to select the appropriate ICG cells based on the architecture and microarchitecture context. An example of sleep scheduling is also described as a simple software-level technique that can be used in conjunction with BTI-Gater to avoid certain pathological aging scenarios. Our experiments show that BTI-Gater can balance the gated clock branches to close to 50 % signal duty ratio, while guaranteeing a glitch-free clock signal with easy-to-verify timing constraints. Results on commercial processors show that BTI-Gater can effectively reduce N/PBTI-induced clock skew of up to 17ps, which can be converted to up to 19.7 % leakage power saving compared to pure design guardbanding. I