On-Chip Self-Awareness Using

The increased demands of high performance, higher power/en-ergy efficiency, and expanding functionality are moving traditional MultiProcessor Systems-on-Chips (MPSoCs) towards heterogenous many-core architectures with hundreds to thousands of cores that need to deal with a diverse and rapid stream of dynamically changing applications with competing and conflicting demands and goals. Fur-thermore, MPSoCs face dramatic manufacturing process variability (as semiconductor technology dives deeper into the nanometer era), and increased vulnerability to environmental and aging effects that induce errors and subsequent faults and failures. In addition, MPSoCs face vexing thermal and heating hazards, creating drastic and harsh environments (e.g., hotspots), that further aggravate aging and wear-out phenomena (e.g., NBTI, HCI, TDDB, Electromigration etc. [1]) resulting in increased susceptibility to errors with the immediate consequence of diminishing yield, reliability and reduced usag