Evaluating the Reuse Cache for mobile processors

Abstract—There has been a lot of research over the years on novel cache architectures to improve cache performance or reduce cache area. However, the focus of these efforts has been on desktop processors and compute workloads. Today, mobile processors represent a significant chunk of the market, and are becoming as complex as their desktop counterparts. Area optimizations are crucial to drive down costs and improve profits in this highly competitive market. Caches, which occupy 20-30 % of the die area of mobile SOCs, are ideal candidates for downsizing. Hence, our work intends to extend the Reuse Cache architecture for use in a mobile processor as it promises reductions in cache size with minimal performance degradation. In this report, we confirm that the observations regarding high percentage of dead lines in the shared Last-Level Cache hold true for mobile workloads running on mobile processors. We propose new techniques to measure the utilization of cache lines to overcome the limitations of the original work. Our version of the reuse cache architecture was implemented in gem5, and the performance was evaluated for several memory-intensive Android applications from the AsimBench mobile benchmark suite. Compared to the baseline model with 4MB conventional L2 cache, our reuse cache design with 1MB data array and 4MB tag array is able to demonstrate 50 % area reductions, 10 % power savings at the cost of only 5 % performance loss. I