With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, re-sulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design in-formation, such that all features (whether critical or non-critical) are treated alike by RET insertion. A recent work [1] proposes to exploit design information (timing slacks) to reduce OPC data vol-ume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC ex-plicitly by timing constraints, w...
Optical Proximity Correction (OPC) has been used for many years now in the semiconductor industry to...
Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in t...
Photolithography has been a key enabler of the aggressive IC technology scaling implicit in Moore's ...
As advanced technology nodes continue scaling down into sub-16 nm regime, optical microlithography b...
As minimum feature sizes continue to shrink, patterned features have become significantly smaller th...
As minimum feature sizes continue to shrink, pattemed fea-tures have become significantly smaller th...
At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) t...
As minimum feature sizes continue to shrink, patterned fea-tures have become significantly smaller t...
In this paper I present the impact of sub-wavelength optical lithography for new EDA tools, IC Layou...
A normal binary chrome mask is designed with optical proximity correction features to test their eff...
It is well known in the industry that the technology nodes from 30nm and below will require model ba...
The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being th...
For a lithography process with a design rule of 0.18 um and beyond, the most critical issue is the g...
The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being th...
The continuous integrated circuit miniaturization and the shrinkage of critical dimension (CD) have ...
Optical Proximity Correction (OPC) has been used for many years now in the semiconductor industry to...
Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in t...
Photolithography has been a key enabler of the aggressive IC technology scaling implicit in Moore's ...
As advanced technology nodes continue scaling down into sub-16 nm regime, optical microlithography b...
As minimum feature sizes continue to shrink, patterned features have become significantly smaller th...
As minimum feature sizes continue to shrink, pattemed fea-tures have become significantly smaller th...
At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) t...
As minimum feature sizes continue to shrink, patterned fea-tures have become significantly smaller t...
In this paper I present the impact of sub-wavelength optical lithography for new EDA tools, IC Layou...
A normal binary chrome mask is designed with optical proximity correction features to test their eff...
It is well known in the industry that the technology nodes from 30nm and below will require model ba...
The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being th...
For a lithography process with a design rule of 0.18 um and beyond, the most critical issue is the g...
The cost per die benefit of semiconductor technology scaling that has driven Moore's law is being th...
The continuous integrated circuit miniaturization and the shrinkage of critical dimension (CD) have ...
Optical Proximity Correction (OPC) has been used for many years now in the semiconductor industry to...
Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in t...
Photolithography has been a key enabler of the aggressive IC technology scaling implicit in Moore's ...