Add to ORKGThis paper presents a novel cache architecture using 7T/14T hybrid SRAM, which can dynamically improve its reliability with control lines. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. The proposed scheme is suitable for dynamic voltage and frequency scaling (DVFS). In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5 V, which is 42 % and 21 % lower, respectively, than the conventional 6T SRAM and the cache word-disable scheme. The respective power reductions are 90 % and 65%
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency ...
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel wo...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRA
SRAM based cache becomes a more critical source of power dissipation, particularly for large last le...
Abstract-this paper proposes a novel Process Variation Aware SRAM architecture designed to inherentl...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
Abstract—In this paper, we present a novel cache scheme which efficiently reduces the minimum operat...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
Increasing demand for implementing highly-miniaturized battery-powered ultra-low-cost systems (e.g.,...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Power density has become the limiting factor in technology scaling as power budget restricts the amo...
© 2014 ACM. Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., be...
Abstract—Power density has become the limiting factor in technology scaling as power budget limits t...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency ...
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel wo...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRA
SRAM based cache becomes a more critical source of power dissipation, particularly for large last le...
Abstract-this paper proposes a novel Process Variation Aware SRAM architecture designed to inherentl...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
Abstract—In this paper, we present a novel cache scheme which efficiently reduces the minimum operat...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
Increasing demand for implementing highly-miniaturized battery-powered ultra-low-cost systems (e.g.,...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Power density has become the limiting factor in technology scaling as power budget restricts the amo...
© 2014 ACM. Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., be...
Abstract—Power density has become the limiting factor in technology scaling as power budget limits t...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency ...
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel wo...