Add to ORKGAn architecture is presented for a digital signal processor (DSP) intended for use in digital mobile phones. In this application, it is necessary to balance the requirement of high processing throughput with the demand of low power for extended battery lifetime. These requirements are addressed by a multi-level power reduction strategy, involving the use of a parallel asynchronous architecture, a configurable compressed instruction set, a large register file, the use of sign-magnitude arithmetic, and reduced support for interrupts. 1
Low-power design can be addressed at different levels of design abstraction such as algorithm, archi...
In battery operated mobile devices there is a growing need for flexible high-performance architectur...
In the last ten years, limited clock frequency scaling and increasing power density has shifted IC d...
Current mobile phone applications demand high performance from the DSP, and future generations are l...
This thesis pertains to the design of a digital signal processor (DSP) with emphasis on lowpower for...
An architecture for a low-power asynchronous DSP has been developed, for the target application of G...
Abstract—This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband...
In this paper, design of an efficient DSP core for telecommunication applications is reported. Time ...
With the explosive growth in portable applications, power efficient computing in a Digital Signal Pr...
Abstract: This paper illustrated the role of Digital Signal Processors (DSP) for third generation mo...
This work presents a methodology for designing an ultra low power application specific instruction s...
In mobile communications, one of the most precious commodities is power. The mobile host can only op...
Over the past couple decades, the capabilities of battery-powered electronics has expanded dra-matic...
Summarization: The advantages of power-aware processors are well known. This paper presents an innov...
Modern cell phones contain various transceivers and their number is expected to increase in the futu...
Low-power design can be addressed at different levels of design abstraction such as algorithm, archi...
In battery operated mobile devices there is a growing need for flexible high-performance architectur...
In the last ten years, limited clock frequency scaling and increasing power density has shifted IC d...
Current mobile phone applications demand high performance from the DSP, and future generations are l...
This thesis pertains to the design of a digital signal processor (DSP) with emphasis on lowpower for...
An architecture for a low-power asynchronous DSP has been developed, for the target application of G...
Abstract—This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband...
In this paper, design of an efficient DSP core for telecommunication applications is reported. Time ...
With the explosive growth in portable applications, power efficient computing in a Digital Signal Pr...
Abstract: This paper illustrated the role of Digital Signal Processors (DSP) for third generation mo...
This work presents a methodology for designing an ultra low power application specific instruction s...
In mobile communications, one of the most precious commodities is power. The mobile host can only op...
Over the past couple decades, the capabilities of battery-powered electronics has expanded dra-matic...
Summarization: The advantages of power-aware processors are well known. This paper presents an innov...
Modern cell phones contain various transceivers and their number is expected to increase in the futu...
Low-power design can be addressed at different levels of design abstraction such as algorithm, archi...
In battery operated mobile devices there is a growing need for flexible high-performance architectur...
In the last ten years, limited clock frequency scaling and increasing power density has shifted IC d...