Design and Implementation of the Ternary Sequences with Good Merit Factor Values

The pulse compression codes with low autocorrelation sidelobe levels and high Merit Factor (MF) are useful in radar, channel estimation and spread spectrum communication applications. One of the main criteria of good pulse compression is MF. A sequence with high MF can be considered as best sequence. In this paper an efficient VLSI architecture is proposed for generation and implementation of the ternary sequences using Finite State Machines [FSM]. This VLSI architecture is implemented on the FPGA as it provides the flexibility of reconfigurability and reprogramability The ternary pulse compression sequence elements are +1,0,-1.Ternary sequences have superior MF compared to binary sequences but cannot be transmitted with existing technology. For transmission of ternary sequences, they must be coded into binary sequences. The binary sequence is chosen such that each of these bi-alphabetic interpretations leads to high MF. At the received section again the received sequence has to be decoded from binary to ternary. The VLSI architecture for implementing ternary codes has been authored in VHDL and the synthesis was done with Xilinx XST, ISE Foundation 12.1i has been used for performing mapping, placing and routing