A Comparative Study: Multiplier Design using Reversible Logic Gates

Abstract — Low power consumption and smaller area are some of the most important criteria for the high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas..Hence in this paper we try to determine the best solution to this problem by using reversible logic gates. reversible logic has emerged as a promising technology having its applications in low power CMOS, Reversible logic circuits have theoretically zero internal power dissipation because they do not lose information, the classical set of gates such as AND, OR, and EXOR are not reversible. The most significant aspect of the reversible gates used in this paper, are that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only.General multiplier is based on two concepts. The partial products can be generated in parallel and thereafter the addition can be reduced by using reversible parallel adder.The entire power analysis can be done using HSPICE tool,and hence by the comparions done we can conclude that the proposed system can reduce the power consumption. Furthermore, it has been demonstrated that the proposed design of reversible multiplier circuit using modified full adder,needs fewer garbage outputs and constant inputs. The multipliers can be generalized for NxN bit multiplication. Thus, this job will be of significant value as the technologies mature