Performance-driven syntax directed synthesis of asynchronous processors

The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthesis paradigm that compiles transparently a system specification written in a high-level language into a network of pre-designed handshaking modules. The trans-parency is provided by a one-to-one mapping from language constructs to the module networks that implement them. This gives the designer flexibility, at the language level, to optimise the resulting circuit in terms of performance, area or power. This paper introduces new techniques that exploit this flexibility to improve the performance of synthesised asyn-chronous systems. The results of a series of transistor level simulations show that these techniques, combined with op-timised handshake module implementations, can produce up to a ten-fold improvement in the performance of a 32-bit, ARM-compatible, asynchronous processor used in an experimental smartcard SoC, without introducing any changes to the original processor architecture.