HIGH SPEED VLSI ARCHITECTURE FOR

Abstract — The basic building blocks of any processor are an adder. But carry generation is difficult in the design of adders. Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers.. In order to reduce the power consumption of a processor we need to reduce number of transistors of the adder. Carry Select Adder is one of the fast adders used in many processors. There is a chance to reduce the area, power and delay in the CSLA structure. The proposed design is implemented by using D-latch along with RCA cascade structure. This paper also presents performance analysis of carry select Adders. The comparison between RCA used CSLA and carry look ahead adder used CSLA is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption. Index terms –D Latches, multiplexers, ripple carr