This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON EDUCATION 1 System-on-Chip Design and Implementation

Abstract—The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant practical work to illustrate the ma-terial taught and is centered around a single design example of a drawing machine. The exercises are composed so that students can regard themselves as part of a design team where they un-dertake the complete design of their own particular section of the system. These design tasks range from algorithmic specification and transaction-level modeling (TLM) of the architecture down to describing the design at the register transfer level (RTL) with sub-sequent verification of their prototype on a field-programmable gate array (FPGA). With this approach, students are able to ex-plore and gain experience of the different techniques used at each level of the design hierarchy and the problems in translating to the next level down. Throughout the module, there is emphasis on using industry standard tools for the modeling and simulation, leading to the use of the SystemC and Verilog hardware descrip-tion languages and Cadence for the simulation environment. Index Terms—Integrated circuit design, large-scale systems modeling, system-level design, system-on-chip, systems engi-neering education, transaction-level modeling (TLM). I