Design of Fir Filter Using Area and Power Efficient Truncated Multiplier

This paper describes the design of Finite Impulse Response (FIR) using the rounded truncated multiplier which offers diminution in area, delay, and power. This anticipated method finally reduces the number of full adders and half adders during the tree reduction in the multiplier block. LSB and MSB is the output form of this multiplier. Deletion, reduction, truncation, rounding and final addition are the operations performed to compress the LSB part. When this scheme is followed the truncation error does not exceeds 1 ulp (unit of least position). So it does not necessitate any error compensation circuits, and the final output will be precised. The proposed filter using truncated multiplier will be designed using VHDL and simulated using ISE Simulator (ISIM).It achieves best area and power result when compared with previous FIR design approaches. General Terms: Digital signal processing, bit width optimization,VLSI design