8 Low Delay Single Error Correction Codes to Protect Data Bits on Memory

Abstract---Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Single error correction (SEC) codes that can correct 1-bit error per word are a common option for memory protection. As technology scales, soft errors on registers also became a concern and, therefore, SEC codes are used to protect registers. The use of an ECC impacts the circuit design in terms of both delay and area. Traditional SEC developed for memories have focused on minimizing the number of redundant bits added by the code. This is important in a memory as those bits are added to each word in the memory. However, for registers used in circuits, minimizing the delay or area introduced by the ECC can be more important. In this paper, a method to construct low delay SEC codes that correct errors only on the data bits is proposed. The method is evaluated for 8 bit data block sizes, showing that the new codes offer significant delay reductions when compared with traditional SEC codes. The results for the area of the encoder and decoder also show substantial savings compared to existing codes. Index Terms—Error correction codes (ECCs), single error correction (SEC), soft errors