Design of Conditional Data Mapping Flip-Flop for Low Power Applications

Abstract—Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24 % reduction of clock driving power is achieved