Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain

Abstract—This work proposes a synthesis process called ‘eTeak ’ which exploits synchronous EDAs to improve the imple-mented circuits. In this regard, it incorporates the synchronous elastic protocol in the Teak synthesis flow to move fine-grained concurrency from the asynchronous into the synchronous domain where clocked CAD tools can optimise the data manipulation units. A transformation technique is also proposed to enable the designer to explore the level of elasticity in the network and trade off the costs associated with computation and communication. I