Controlled Ring Oscillator

Abstract-- This work describes a two-stage CMOS Voltage Ring Oscillator (VCRO) using differential delay cells are analyzed. The main aim of the paper is to increase the tuning range of the circuit and obtain a good phase noise at the cost of design complexity and power consumption. Two-stage VCRO implemented in 90 nm Technology realizes a tuning range of 53.40 % and a phase noise of-156.328 dBc/Hz for a power consumption of 9.85mW. The phase noise of the VCRO is bettered by cascading more number of stages to trade off power consumption A four-stage VCRO is implemented and achieved a tuning range of 62.15 % and a phase noise of-116.608 dBc/Hz. However the power consumption of the circuit increased to 16.45mW