MTCMOS DESIGN FOR EFFECTIVE VOLTAGE DROP CONTROL

Abstract — Power reduction is one of the most significant challenges in designing today’s advanced VLSI circuits. Power gating is a technique used in IC design to reduce power consumption by shutting off the current to parts of the circuits which are not in use. In MTCMOS, the large inrush current and ramp up time are arised. We are proposing a new analytical model considering package RLC parasitic for reducing the inrush current and ramp up time. It is possible by analyzing the impact of decoupling capacitances on ramp up time and inrush current. Unlike the previous power sequence method, we are proposing a different inrush current modeling. We can consider our framework as a conservative method to limit the inrush current. So the power up sequence generated by our proposed method can satisfy the inrush current constraint