Abstract- An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired OR scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs).Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low operations(531 MHz at 0.6 V) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 nm process technology, as much as 16.4 % in operation speed and ...
AbstractIn this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circ...
This paper presents a novel circuit design technique to reduce the power dissipation in sequential c...
Abstract: Two innovative high-speed low power parallel 8-bit counter architectures are proposed. The...
An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply volt...
New design improvement aiming to reduce the power consumption of true single-phase clock-based dual-...
In this paper the power consumption and operating frequency of true single phase clock (TSPC)...
Dual-modulus prescaler is a critical block in power conscious PLL design. By modifying the second br...
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E...
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-...
A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual mod...
This paper enumerates a low power, high speed design of flip-flop having less number of transistors....
The performance of integrated circuits is evaluated by their design architecture, which ensures high...
True single-phase clock (TSPC) rationale has discovered broad use in digital design. Initially as a ...
In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit desi...
AbstractIn this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circ...
This paper presents a novel circuit design technique to reduce the power dissipation in sequential c...
Abstract: Two innovative high-speed low power parallel 8-bit counter architectures are proposed. The...
An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply volt...
New design improvement aiming to reduce the power consumption of true single-phase clock-based dual-...
In this paper the power consumption and operating frequency of true single phase clock (TSPC)...
Dual-modulus prescaler is a critical block in power conscious PLL design. By modifying the second br...
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E...
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-...
A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual mod...
This paper enumerates a low power, high speed design of flip-flop having less number of transistors....
The performance of integrated circuits is evaluated by their design architecture, which ensures high...
True single-phase clock (TSPC) rationale has discovered broad use in digital design. Initially as a ...
In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit desi...
AbstractIn this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circ...
This paper presents a novel circuit design technique to reduce the power dissipation in sequential c...
Abstract: Two innovative high-speed low power parallel 8-bit counter architectures are proposed. The...