Design of a Low Power Level-up Shifter in Multi Supply Voltage Design using MTCMOS Technique

Abstract — Level shifter is an interfacing circuit which can interface low core voltage to high input-output voltage. It allows communication between different modules without adding up any extra supply pin. It is a key circuit component in multi-voltage circuits. The main objective of the work is to minimize power dissipation in shifter circuit, which is due to different supply voltages in the circuit. The proposed method uses MTCMOS technique, which is one of the low power design technique to achieve power minimization. The model presents a new low-power level shifter (LS) for logic voltage shifting from sub-threshold to above-threshold domain. The new circuit uses the multi-threshold CMOS technique to provide a wide voltage conversion. The proposed design is implemented in CADENCE Virtuoso 180-nm CMOS technology process which converts 230-mv input signals into 3-V output signals. The new LS reaches a propagation delay value of 17 ns, a static power dissipation of only 115.3 pW, for a 1-MHz input pulse