Predicting Multiprocessor Memory Access Patterns with Learning Models

A neural network based technique is introduced which hides the control latency of reconfigurable interconnection networks (INS) in shared memory multiprocessors. Such INS require complex control mechanisms to reconfigure the IN on demand, in order to satisfy processor-memory accesses. Hiding the control latency seen by each access improves multiprocessor performance significantly. The new technique hides control latency by employing a time-delay neural network (TDNN) as a prediction technique that learns the current processor-memory access patterns and predicts the need to reconfigure the IN. Training and prediction of the TDNN is performed on-line. Based on three experiments, the TDNN is able to learn repetitive patterns and predict the need to reconfigure the IN thus, effectively hiding control latency of processor-memory accesses.