SENIC: Scalable NIC for End-Host Rate Limiting

Rate limiting is an important primitive for managing server network resources. Unfortunately, software-based rate limiting suffers from limited accuracy and high CPU overhead, and modern NICs only support a handful of rate limiters. We present SENIC, a NIC design that can natively support 10s of thousands of rate limiters—100x to 1000x the number available in NICs today. The key idea is that the host CPU only classifies packets, en-queues them in per-class queues in host memory, and specifies rate limits for each traffic class. On the NIC, SENIC maintains class metadata, computes the transmit schedule, and only pulls packets from host memory when they are ready to be transmitted (on a real time basis). We implemented SENIC on NetFPGA, with 1000 rate lim-iters requiring just 30KB SRAM, and it was able to accu-rately pace packets. Further, in a memcached benchmark against software rate limiters, SENIC is able to sustain up to 250 % higher load, while simultaneously keeping tail latency under 4ms at 90 % network utilization.