The Silent Transistor: A New Topology for Low

Abstract — This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a novel low-leakage technique The silent transistor. The silent transistor technique is applied to memory cells, and achieve between two and three orders of magnitude leakage power reduction compared to the best prior state saving technique we could find (namely, the forced stack technique)power consumption cannot be overstressed. Index Terms — sleepy stack, silent transistor, low leakage power dissipation, SRAM cell. I