Built-in Self Repair for SRAM Array using Redundancy

Abstract—In this paper, a built-in self repair technique for word-oriented two-port SRAM memories is presented. The technique is implemented by additional hardware design instead of traditional software diagnostic procedures and the computation time is minimized. A built-in self-test (BIST) is used to detect the faulty locations which are isolated immediately after detection. Therefore, the redirection process can be executed as soon as possible. Spare rows are used to replace the faulty rows. The hardware overhead of the automatic fault isolation design depends on size of memory system. All the repairs using BISR circuit are done at power on. Index Terms—SRAM, two-port memories, PVT faults, fault isolation, BISR I