Dynamic, Multi-Core Cache Coherence Architecture for Power-Sensitive Mobile Processors

Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. However, these mobile processors are also expected to be compact, ultra-portable, and provide an always-on, contin-uous data access paradigm necessitating a low-power design. As mobile processors increasingly begin to leverage multi-core functionality, the power consumption incurred from main-taining coherence between local caches due to bus snooping becomes more prevalent. This paper explores a novel ap-proach to mitigating multi-core processor power consumption in mobile smartphones. By using dynamic application mem-ory behavior, one can intelligently target adjustments in the cache coherency protocol to help reduce the overhead of main-taining consistency when the benefits of multi-core shared cache coherence are muted. On the other hand, by utilizing a fine-grained approach, the proposed architecture can still re-spond to and enable the benefits of hardware cache coherence in situations where the performance improvements greatly outweigh the associated energy costs. The simulation results show appreciable reductions in overall cache power consump-tion, with negligible impact to overall execution time