Novel Anti Punch doping in Recessed Source Drain UTB SGOI MOSFETs for Reduced Static

Abstract — An evaluation of the Recessed Source Drain Silicon-Germanium on Insulator (SGOI) MOSFETs is reported by implementing a 2D device design flow using a commercial Technology CAD (TCAD) tool within the context of optimizing the device design for low leakage and low static power dissipation in circuits. These devices have been explored with an aim to continue the trend of scaling and also to improve the device performance with respect to delay and power dissipation. In this paper, the improvement in static leakage in CMOS circuits achieved by introducing Anti-Punch (AP) doping in conventional Recessed Source drain Silicon- Germanium on Insulator (SGOI) MOSFETs is presented. Device doping profiles have been optimized to obtain minimum leakage and minimum static power dissipation. Static leakage in devices with AP is suppressed (83 % in both NMOS and PMOS devices) due to reduced short channel effects leading to reduced sub threshold leakage currents. This results in an average power savings of 67 % in Ring Oscillator (RO) built using the newly proposed devices. However, the delay in the AP RO increases by 11 % because of reduction in on current (11.9 % in NMOS and 8 % in PMOS)