www.iord.in Page 47 Delay & Area Efficient Carry-Select Adder

Abstract — In this paper, the logic operations occupied in conventional carry select adder (CSLA) and BEC-based carry select adder (CSLA) i.e., binary to excess-1 converter based carry select adder are estimated to study the data dependence and to identify redundant logic operations. We have removed all the redundant logic operations included in the conventional CSLA and proposed a new logic formation for CSLA. In the proposed idea, the carry select (CS) function is planned before the calculation of final-sum which is unlike from the conventional approach. Bit patterns of two expecting carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. A capable CSLA design is obtained using improved logic units. The proposed carry select adder (CSLA) design involves considerably less area and delay than the recently proposed BEC-based carry select adder. Due to the slight carry-output delay, the proposed CSLA design is a good nominee for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35 % less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is finest between the existing SQRT-CSLA designs, for the different input bit-widths. I