Asynchronous Implementation of Split-radix FFT Algorithm Using FPGA

Abstract—The Fast Fourier Transform (FFT) finds a variety of applications particularly in the field of communication engineering. The Split Radix FFT (SRFFT) is one of the very many algorithms to compute FFT. In this paper, we propose a completely asynchronous design of the split-radix FFT processor core with absolutely no glitches at the output. It reduces the system latency drastically. The asynchronous design makes sure that there is no separate data load stage in the processor. The reading of the output and the loading of the new inputs can be done simultaneously. This helps to improve the speed of the device. Further, we present an algorithm to reduce the number of ROMs to store the twiddle factors