Add to ORKGSelf-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%. 1
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, c...
Abstract. Circuit realization in one PLA may be unacceptable because of the large number of terms in...
Self-timed circuits present an attractive solution to the problem of process variation. However, imp...
A novel synthesis method for self-timed realization of arbitrary combinational logic functions is pr...
Self-timed circuits present an attractive solution to the problem of process variation. However, imp...
This paper presents a technique for efficient gate-level realization of strongly indicating function...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
ARTICLE IN PRESS Self-timed logic design methods are developed using Threshold Combinational Reducti...
Objective of this paper is to present historiography of logic switching circuits. The research mainl...
A computer-aided design procedure for the minimization of multiple-output Boolean functions as encou...
This paper presents a technique to determine prime implicants in multi-level combinational networks....
We present a system for simultaneously synthesizing and proving correct CMOS implementations of comb...
[[abstract]]The use of communication complexity based logic synthesis when configuring programmable ...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, c...
Abstract. Circuit realization in one PLA may be unacceptable because of the large number of terms in...
Self-timed circuits present an attractive solution to the problem of process variation. However, imp...
A novel synthesis method for self-timed realization of arbitrary combinational logic functions is pr...
Self-timed circuits present an attractive solution to the problem of process variation. However, imp...
This paper presents a technique for efficient gate-level realization of strongly indicating function...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
ARTICLE IN PRESS Self-timed logic design methods are developed using Threshold Combinational Reducti...
Objective of this paper is to present historiography of logic switching circuits. The research mainl...
A computer-aided design procedure for the minimization of multiple-output Boolean functions as encou...
This paper presents a technique to determine prime implicants in multi-level combinational networks....
We present a system for simultaneously synthesizing and proving correct CMOS implementations of comb...
[[abstract]]The use of communication complexity based logic synthesis when configuring programmable ...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, c...
Abstract. Circuit realization in one PLA may be unacceptable because of the large number of terms in...