A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC platform for Embedded Applications

Abstract—Modern embedded systems are built around the soft core processors implemented on FPGA. The FPGAs being capable of implementing custom hardware blocks giving the advantage of ASICs, and allowing the implementation of processor platform are resulting in powerful Configurable-system on chip(C-SoC)platforms. The Microchip’s PIC microcontroller is very widely used microcontroller architecture across various embedded systems. The implementation of such core on FPGA is very much useful in CSOC based embedded systems. This type of designs can be widely used in those controlling fields demanding low power consumption and high ratio of performance to price. In this project a reduced instruction set computer (RISC) CPU IP core whose instructions are compatible with the Microchip PIC16C6Xseries of microcontrollers is implemented in VHDL. The core is based on 8-bit RISC architecture and top-Down design methodology is used in developing the core. The RISC CPU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-stage instruction pipeline. The architecture will be designed aiming at single cycle execution of the instructions, except those related to program branches. Since this type of CPU based on RISC architecture, there are only 35 reduced instructions in its instruction set, which are easy to be learned and used. The performance of the 8-bit RISC CPU is better than those of CPUs which are based on CISC architecture. Modelsim Xilinx Edition (MXE) will be used simulation and functional verification. The Xilinx Spartan-3E FPGAs will be used synthesis and timing analysis. The results will be verified on chip with chipscope tool