A Novel Methodology to Implement Viterbi Decoder Using FPGA

Abstract: Bandwidth and power is the most important parameter in every communication system. So the maximum utilization of bandwidth and minimum useful usage of power is achieved with error detection and correction methods. In satellite &space communication channel capacity is degraded as a result of Additive White Gaussian Noise, which are mostly random. Convolutional encoder with Viterbi decoder is a random error correction method with small constraint length and memory. Viterbi algorithm is a dynamic programming method which maintains the reliability and allows transmission of information quickly and accurately. Without retransmission it will provide maximum accuracy and reliability with low power consumption. It reduces error probability to almost closer to theoretical bounds, so it can be use maximum bandwidth for our application. FPGA acts as memory for the working of Viterbi decoder which adds design flexibility and adaptability with optimal device utilization. It conserving the system power, speed and board space