Network Processor based Router and the Cache Design: Implementation and Evaluation

Abstract—High performance routers are mostly implemented with network processors because of their software programmability, hardware computation power, and high bandwidth interface design. In this paper, a 5-dimensional packet classification algorithm based on the hierarchal binary prefix search is first implemented in IXP1200 network processor. Our classification implementation is faster and smaller than other existing schemes and makes it possible to put entire rule table in SRAM. Moreover, we proposed a cache mechanism for IXP1200 because we observed that the traffic patterns of backbone routers have a strong temporal locality. Our proposed cache scheme not only caches the results from packet classification but also caches the results from IP lookups. Only one SRAM read is needed to perform IP lookups and packet classification for a cache hit. With this cache mechanism, the throughput of our system is very close to the theoretical maximum bandwidth with a reasonable hit ratio. Specifically, with a cache of 8192 rule entries, the proposed cache mechanism has 50 % improvement in throughput over the system with no cache. Keywords—IXP1200 network processor, binary prefix search, IP lookups, packet classification, and cache..