Add to ORKGAbstract- A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40PW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.
The objects of research are processes in electrical scheme and enormous digital control systems in c...
The consumer market is increasing its demand for battery-operated portable devices. Due to the high ...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
An integrated CMOS voltage-mode buck dc-dc converter with on-chip pulse-width modulation (PWM) techn...
Cascode architecture is an efficient and cost effective design technique to overcome the reliability...
Abstract—A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage ...
Abstract—This paper presents a 0.6 V input, 0.3–0.55 V output buck converter in 40 nm CMOS, for low-...
A pseudo-digital pulsewidth modulation (P-DPWM) controlled boost direct current-direct current conve...
With IC technology scaling into the deep sub-micron region, circuit power dissipation has become a p...
The integration of DC-DC converter in standard CMOS process faces challenges from the low transistor...
Level shifter is an important building block in the power management system. In the DC-DC buck conve...
Level shifter is an important building block in the power management system. In the DC-DC buck conve...
This paper presents the implementation of the buck-boost converter design which is a power electroni...
In this paper we present an asynchronous finite-state machine digital controller co-integrated with ...
This paper is descried about a proposed scheme of a low-cost digital pulse width modulation (DPWM) c...
The objects of research are processes in electrical scheme and enormous digital control systems in c...
The consumer market is increasing its demand for battery-operated portable devices. Due to the high ...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
An integrated CMOS voltage-mode buck dc-dc converter with on-chip pulse-width modulation (PWM) techn...
Cascode architecture is an efficient and cost effective design technique to overcome the reliability...
Abstract—A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage ...
Abstract—This paper presents a 0.6 V input, 0.3–0.55 V output buck converter in 40 nm CMOS, for low-...
A pseudo-digital pulsewidth modulation (P-DPWM) controlled boost direct current-direct current conve...
With IC technology scaling into the deep sub-micron region, circuit power dissipation has become a p...
The integration of DC-DC converter in standard CMOS process faces challenges from the low transistor...
Level shifter is an important building block in the power management system. In the DC-DC buck conve...
Level shifter is an important building block in the power management system. In the DC-DC buck conve...
This paper presents the implementation of the buck-boost converter design which is a power electroni...
In this paper we present an asynchronous finite-state machine digital controller co-integrated with ...
This paper is descried about a proposed scheme of a low-cost digital pulse width modulation (DPWM) c...
The objects of research are processes in electrical scheme and enormous digital control systems in c...
The consumer market is increasing its demand for battery-operated portable devices. Due to the high ...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...