Add to ORKGAbstract — Contention-less flip-flops (CLFF’s) and separated power supply voltages (VDD) between flip-flops (FF’s) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU’s by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved
A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by u...
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design al...
In the present day microelectronics, supply voltage scaling has received an intense attention as an ...
Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design tech...
Abstract: In this paper, implementations of the flip-flops are presented which are level triggered a...
The increasing demand of portable applications motivates the research on low power and high speed ci...
In integrated circuits, power consumption is a one of the top three challenges like area, power and ...
With the evolution of the semiconductor industry and the continuous growing demands for high perform...
With the evolution of the semiconductor industry and the continuous growing demands for high perform...
Optimization of power is always one of the most important design objectives in the modern ICs. In th...
The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduc...
The aggressive CMOS technology shrinking driven by cost reduction, performance improvement and power...
Energy performance requirements are forcing designers of next-generation systems to explore approach...
textLow-power digital design has been a widely researched area for the past twenty years. The grow...
With the vast advancement in VLSI technology, tens of millions of transistors are integrated on a si...
A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by u...
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design al...
In the present day microelectronics, supply voltage scaling has received an intense attention as an ...
Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design tech...
Abstract: In this paper, implementations of the flip-flops are presented which are level triggered a...
The increasing demand of portable applications motivates the research on low power and high speed ci...
In integrated circuits, power consumption is a one of the top three challenges like area, power and ...
With the evolution of the semiconductor industry and the continuous growing demands for high perform...
With the evolution of the semiconductor industry and the continuous growing demands for high perform...
Optimization of power is always one of the most important design objectives in the modern ICs. In th...
The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduc...
The aggressive CMOS technology shrinking driven by cost reduction, performance improvement and power...
Energy performance requirements are forcing designers of next-generation systems to explore approach...
textLow-power digital design has been a widely researched area for the past twenty years. The grow...
With the vast advancement in VLSI technology, tens of millions of transistors are integrated on a si...
A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by u...
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design al...
In the present day microelectronics, supply voltage scaling has received an intense attention as an ...