A Novel Iterative Threshold for Anti-jamming Algorithm and Its Implementation on FPGA

Abstract — Frequency-domain anti-jamming (FDAJ) algorithms achieve prominent performance on interference suppression with simple calculations; and hence they are widely used in many applications. The interference suppression threshold plays a key role in the algorithm and affects system performance greatly. In this paper, the initial interference threshold is derived theoretically and then a novel FDAJ algorithm is proposed based on the iterative calculation of the threshold. With the iterative process, the optimal threshold for the interference suppression can be approached with little loss of valid signals; and the anti-jamming performance can be further improved. The simulation results validate well that our proposed iterative algorithm has superior performance for interference suppression. Finally, two FPGA-based implementations are presented: pipeline scheme and iterative scheme. After analysing the different characteristics of each implementation, we discuss the suitable applications for these schemes