Low cost debug architecture using lossy compression for silicon debug

The size of on-chip trace buffers used for at-speed sili-con debug limits the observation window in any debug ses-sion. Whenever the debug experiment can be repeated, we propose a novel architecture for at-speed silicon debug that enables a methodology where the designer can iteratively zoom only in the intervals containing erroneous samples. When compared to increasing the size of the trace buffer, the proposed architecture has a small impact on silicon area, while signicantly reducing the number of debug sessions. 1