Time-Constrained Clustering for DSE of Clustered VLIW-ASP

In this paper we describe a new time-constrained clus-tering algorithm. It is coupled with a time-constrained scheduling algorithm and used for Design-Space-Explo-ration (DSE) of clustered VLIW processors with heteroge-neous clusters and heterogeneous functional units. The algorithm enables us to reduce the complexity of the DSE, because the parameters of the VLIW are derived from the clustered schedule of the considered application which is produced during a single compilation step. Several com-pilations of the same application with different VLIW-parameter settings are not necessary. Our proposed algo-rithm is integrated into a DSE-Tool in order to explore the best parameters of a clustered VLIW processor for several basic blocks of signal processing applications. The obtained results are compared to the results of Lapinskii's work and show, that, for most benchmarks, we are able to save ports in the register file of each cluster. 1