IMPLEMENTATION OF MODIFIED TEST PATTERN GENERATOR FOR BIST APPLICATION

In recent years, with the advance of digital Very Large Scale Integrated (VLSI) circuits, manufacturing and testing have led to many challenges. A digital system is diagnosed and tested several times during its lifetime. So in digital systems testing of digital circuits play key role. Built-in-Self-Testing (BIST) is a demanding technique for testing of digital circuits. Therefore, it becomes attractive option to build the self-test function into the hardware. In BIST different kind for test pattern generator are used to generate pattern, generated pattern is applied to the circuit-under-test (CUT).Linear feedback shift register is most attractive technique for pattern generation. Power dissipation is high in normal LFSR due to internal switching. In this paper we implement a modified LFSR in BIST architectures. Modified LFSR is designed by using 2x1 multiplexer and normal LFSR. This modified LFSR is called Bit-Swapping LFSR (BS-LFSR).It shows reduction in power due to limited internal transition