Efficient Built-in Self Repair Analyzer for Embedded word oriented SRAM and DRAM Memories with selectable redundancy

Abstract- This paper proposes Built-In Self-Repair Analyzer (BISR) strategy with Redundancy which is an effective yield-enhancement strategy for embedded memories. It consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible so that it can provide four operation modes to SRAM users. The feature of the proposed BISR strategy is that it can save each fault address for only once.To achieve a high repair speedin BIAA module, fault addresses and redundant ones form a one-to-one mapping. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy. This paper proposes BISR strategy for DRAM also. Advantage of Proposed Work is that the BISR can perform bit oriented and word oriented memory analyzing and also it supports self-repair strategy with selectable redundancy. In the existing paper BISR is implemented for only SRAM, whereas the proposed paper extended it to DRAM. We design word oriented SRAM and DRAM and implement BISR analyzer with selectable redundancy. The selectable redundancy will provide the advantage of low area, low complexity and flexible to compiler designs