Analysis and Evaluation of Greedy Thread Swapping Based Dynamic Power Management for MPSoC Platforms

Abstract — Thread migration (TM) is a recently pro-posed dynamic power management technique for heteroge-neous multi-processor system-on-chip (MPSoC) platforms that eliminates the area and power overheads incurred by fine-grained dynamic voltage and frequency scaling (DVFS) based power management. In this paper, we take the first step towards formally analyzing and experimen-tally evaluating the use of power-aware TM for parallel data streaming applications on MPSoC platforms. From an analysis perspective, we characterize the optimal mapping of threads to cores and prove the convergence properties of a complexity effective greedy thread swapping based TM algorithm to the globally optimal solution. The proposed techniques are evaluated on a 9-core FPGA based MPSoC prototype equipped with fully-functional TM and DVFS support, and running a parallelized video encoding bench-mark based on the Motion Picture Experts Group (MPEG-2) standard. Our experimental results validate the pro-posed theoretical analysis, and show that the proposed TM algorithm provides within 8 % of the DVFS performance under the same power budget, and assuming no overheads for DVFS. Assuming voltage regulator inefficiency of 80%, the proposed TM algorithm has 9 % higher performance than DVFS, again under the same total power budget