LOW POWER SEQUENTIAL ELEMENTS FOR MULTIMEDIA AND WIRELESS COMMUNICATION APPLICATIONS

In integrated circuits, power consumption is a one of the top three challenges like area, power and speed. Power optimization of IC’s can be achieved in gate level, logical level, algorithmic level and circuit level (transistor level). From these levels one of the best optimization is transistor level, because the structure of the transistor will play a major role in power dissipation. Practically, clocking system consumes large portion of total chip power which consists of clock distribution network and flop-flops. Various design techniques are available to reduce the flip flop power. In this paper removal of noise coupling transistor approach is implemented in new flip flop then further power reduction is carried out by employing already existing methods like double edge triggering and SVL method. Based upon those techniques, the proposed flip flops in this paper having improved power reduction capability than existing flip flop by 6%~90 % and improved PDP by 9%~90%. Some of the proposed flip flops are used in multimedia and error detector application