AN EXPLICIT CROSSTALK AWARE DELAY MODELLING FOR ON-CHIP VLSI RLC INTERCONNECT WITH SKIN EFFECT

This paper presents a novel analytical closed form expression for the crosstalk noise voltage and delay in the presence of skin effect. With the rapid development of high frequency IC technology, a number of high-speed interconnect effects, such as ringing, signal delay, distortion, reflections, and crosstalk, need to be considered during the IC design. Skin effect is one of the high frequency phenomena that can adversely affect the distribution of current density in interconnect because the problem associated with the skin effect is that it attenuates the high frequency components of a signal more than that of the low frequency components. On-Chip interconnect has become the dominant factor in deep sub-micrometer (DSM) integrated circuits (ICs). With increasing levels of on-chip integration, more functional units are integrated onto a single die, such as a multi-core microprocessor and a system-on-chip. Global interconnect, which acts as a communication media among these functional units, plays an increasingly important role and can significantly limit the performance of advanced systems. Accurate noise and delay modelling for RLC lines is thus critical for timing and signal integrity analysis. Skin effect basically affects the resistance and also the inductance, which in turn affects the system integrity in particular and its response as a whole. The current distribution inside the conductor changes as frequency increases. These changes produced in the conductors are known as skin effect. Till now the skin effect has been neglected for the modelling of the on-chip interconnects. But with the increase in frequency to the GHz range, the skin effect has become prominent in performance parameter modelling. In this paper, firstly a crosstalk noise formula for on chip VLSI interconnect has been proposed without considering the skin effect. The voltage response at the output node i