Challenges of WCET Analysis in COTS Multi-core due to Different Levels of Abstraction

www.fortiss.org Abstract. The continuous demand of producing low cost multi-core hardware for safety critical hard real time applications has driven at-tempts of using Commercial Off The Shelf (COTS) components. Prior to the industrial deployment, Worst Case Execution Time (WCET) of these applications must be estimated on underlying hardware. However, even simple COTS components exhibit unpredictability at very low level which render them not suitable for conservative timing analysis. These low level unpredictability, implied from hardware specifications, are mostly invisi-ble to MPSoC integrator and WCET tool manufacturers due to abstrac-tion. Additionally, predictable hardware designers propose advance tech-niques for predictable and high performance multi-core systems ignoring abstraction that tool manufactures use. The combination of such advance hardware and abstraction enforces investigation of all paths through ap-plication execution. As contribution, this paper identifies two low level unpredictability de-duced from COTS interconnect specifications which render them unsuit-able for WCET analysis in multi-core environment. Moreover, the paper also shows that the advance arbitration scheme, budget based arbitra-tion, invented for better predictability and performance prevents WCET tool to apply state space reduction and enforces analysis of all paths.