VERIFICATION ANALYSIS OF AHB-LITE PROTOCOL WITH COVERAGE

The SoC design faces a gap between the production capabilities and time to market pressures. The design space, grows with the improvements in the production capabilities in terms of amount of time to design a system that utilizes those capabilities. On the other hand shorter product life cycles are forcing an aggressive reduction of the time-to-market. Fast simulation capabilities are required for coping with the immense design space that is to be explored; these are especially needed during early stages of the design. This need has pushed the development of transaction level models, which are abstract models that execute dramatically faster than synthesizable models. The pressure for fast executing models extends especially to the frequently used and reused communication libraries. The presents paper describes the system level modelling of the Advanced High-performance Bus Lite (AHB-Lite) subset of AHB which part of the Advanced Microprocessor Bus Architecture (AMBA). The work on AHB-Lite slave model, at different test cases, describing their simulation speed. Accuracy is built on the rich semantic support of a standard language SystemVerilog on the relevant simulator Riviera has been highlighted