An undersampling 14-bit cyclic ADC with over 100-dB SFDR

Abstract: A high linearity, undersampling 14-bit 357 kSps cyclic analog-to-digital convert (ADC) is designed for a radio frequency identification transceiver system. The passive capacitor error-average (PCEA) technique is adopted for high accuracy. An improved PCEA sampling network, capable of eliminating the crosstalk path of two pipelined stages, is employed. Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area. An additional digital calibration block is added to compensate for the error due to defective layout design. The presented ADC is fabricated in a 180 nm CMOS process, occupying 0.65 1.6 mm2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range (SFDR), and the peak SFDR is as high as 106.4 dB with 2.431 MHz input. Key words: cyclic ADC; high linearity; undersampling; improved passive capacitor error-average sampling network; opamp sharing DOI: 10.1088/1674-4926/31/2/025008 EEACC: 1290B; 1280; 1205 1